The heart of any microprocessor, microcontroller, or data-acquisition system lies in its clock circuitry, which provides critical timing information to the various subsystems. In many applications—for example, data acquisition systems—the components experience long wait periods punctuated by brief periods of high-load activity. In such cases, it is desirable to save power by switching the clock speed between two modes of operation, i.e., by reducing the clock frequency during wait mode, then increasing the clock to a normal, fast frequency during heavy load conditions.
Currently known methods of implementing this power saving method are unsatisfactory in a number of respects. For example, when these systems switch to a slower clock frequency, the user is unable to keep time (i.e., real time) because the timers are then running at different speeds. One prior art solution to this problem involves implementing an additional real time clock source. This solution, however, greatly increases power consumption and cost.
Furthermore, most prior art devices use a phase-locked loop (PLL) to switch between different clock frequencies, leading to undesirable jitter on the clock line. This jitter affects and can even disable communication between other devices in the system.